1. Field of the Invention
The present invention relates to a grinding method for semiconductor wafers. More particularly, it relates to a wafer grinding method suited to large silicon wafers having a diameter of about 450 mm that employ a carrier to simultaneously grind both sides of a wafer between upper and lower surface plates. The present invention further relates to a semiconductor grinding surface plate and device suitable for use in the above method.
2. Discussion of the Background of the Invention
In the simultaneous grinding of both surfaces of a wafer during the manufacturing of a semiconductor wafer from silicon or the like, anywhere from 1 to as many as about 10 workpieces (semiconductor wafers) are generally inserted into the carrier holding the work for grinding. The number of workpieces varies based on factors such as increasing productivity relating to device size, work diameter and the like; specifications that take into account the work track and permeation of abrasive solution; and the like.
Planetary gear-type devices can be employed in such grinding of both surfaces of semiconductor wafers. However, when a planetary gear-type grinding device is employed, outer circumference sagging (peripheral sagging) occurs, resulting in precluding the obtaining of wafers with a high degree of flatness. As a countermeasure to outer circumference sagging, a method seeking to improve flatness through carrier design is proposed in Japanese Unexamined Patent Publication (KOKAI) No. 2002-254299, which is expressly incorporated herein by reference in its entirety. This method is a technique (fixed dimension polishing) in which the thickness of a carrier is controlled with a high degree of precision so as to approach the final thickness of the work, to disperse stress acting on the outer circumference portion of the work into the carrier to obtain a flat work.
However, the method described in Japanese Unexamined Patent Publication (KOKAI) No. 2002-254299 does not prevent peripheral sagging of wafers.
Accordingly, the present inventors conducted extensive research into the relation between semiconductor wafers as works and the stress that acts on the carrier holding the semiconductor wafers. As a result, they discovered that by conducting polishing with a carrier in which the circle radius (PCD), which specifies the spacing of the holes as the radius of a circle passing through the center of the holes in the carrier, and/or in which the spacing between works, was set to within a prescribed range, it was possible to evenly disperse the pressure from the surface plates in the surface of the wafers to prevent peripheral sagging of wafers without diminishing productivity and without shortening the service life of the carrier.
The solution that was discovered was in the form of a device for polishing both surfaces of semiconductor wafers including a pair of upper and lower rotating surface plates; a sun gear provided in a rotating center portion between the upper and lower rotating surface plates; a ring-shaped inner-toothed gear positioned on an outer circumference portion between the upper and lower rotating surface plates; and a carrier made of a planetary gear, the planetary gear meshing with the inner-toothed gear and sun gear and being positioned between the upper and lower rotating surface plates, wherein the carrier has multiple holes serving as holes receiving wafers being polished, and centers of the multiple holes are positioned on a circumference of a single circle, with a ratio of an area of a circle passing through the centers of the multiple holes to an area of one of the wafers being polished greater than or equal to 1.33 but less than 2.0, and the above device is described in Japanese Unexamined Patent Publication (KOKAI) No. 2009-4616, published on Jan. 8, 2009, which is expressly incorporated herein by reference in its entirety.
A method of grinding semiconductor wafers including simultaneously polishing both surfaces of multiple semiconductor wafers being polished by rotating the multiple semiconductor wafers between a pair of upper and lower rotating surface plates in a state where the multiple semiconductor wafers are held on a carrier so that centers of the multiple semiconductor wafers are positioned on a circumference of a single circle, wherein a ratio of an area of a circle passing through the centers of the multiple semiconductor wafers to an area of one of the multiple semiconductor wafers is greater than or equal to 1.33 but less than 2.0, is also discussed in above-described Japanese Unexamined Patent Publication (KOKAI) No. 2009-4616.
The size of the silicon wafers cut from single crystals of silicon is increasing in an about a 10-year cycle. Device manufacturers hope to increase device manufacturing efficiency by increasing the size of the silicon wafers. In light of these circumstances, the manufacturing of silicon wafers with diameters of about 450 mm, about 1.5 times the current diameter of 300 mm, is planned for the near future.
Polishing of silicon wafers 450 mm in diameter will involve polishing of an area that is double or more that of conventional silicon wafers equal to or less than 300 mm in diameter. Thus, difficulty is anticipated in obtaining silicon wafers with the same flatness as in the past while maintaining production efficiency by the same method as before.
In particular, for silicon wafers 450 mm in diameter, it is difficult to obtain silicon wafers of the same flatness as in the past while maintaining production efficiency by the conventionally employed combination of lapping with free abrasive grains and grinding with fixed abrasive grains.
Mainstream conventional processing machinery includes an inner circumference gear and an outer circumference gear. With such machinery, there is a concern that quality will deteriorate due to differences in peripheral speed of the inner and outer circumferences.
In the semiconductor wafer polishing device in the above patent application, there is a mechanism that does not include an inner circumference gear, making it possible to increase the size of the device as the size of the wafer increases. Further, the wafer itself oscillates to cover the difference in peripheral speed of the inner and outer circumferences, and various pellets are arranged in individual areas of the wafer based on the dimensions of the surface plates and the like.